1. Field of the Invention
The invention generally relates to field programmable gate arrays (FPGAs) and more particularly to the programming of FPGAs, and even more particularly with programming of embedded FPGAs (EFPGAs).
2. Prior Art
In today's world the use of integrated circuits (ICs) is ubiquitous, and they can be found in practically every device, even in the regular household. A particular branch of ICs is that of field programmable gate arrays (FPGAs) which are designed to be configured in the field, using some kind of a hardware description language (HDL). The language describes the specific configuration of components of the FPGA so that it is operated as desired by a user making use of the IC. One of the main advantages of FPGAs is the ability to perform partial or full reconfiguration of the device even when it is already connected as part of a system, if such capabilities are kept enabled for the device. In certain cases, reconfiguration takes place as part of the normal operation of the device as it may be necessary to perform different functions at different times.
In some cases FPGAs have therein embedded components such as microprocessors, and other peripheral devices to provide enhanced functionality. This integration leads to lower costs and reduced failures of the system. In other cases, certain ICs integrate therein features of FPGAs, creating embedded FPGAs (EFPGAs) to allow a certain degree of flexibility to a user to customize a component in a way that fits specific user design needs. Regardless of which FPGA is used, the challenge of the FPGA is in its programming that is a combination of a program and hardware support to allow the FPGA to be configured as desired. Such programming support in the prior art has a significant overhead associated thereto, which is a problem, especially in the case of EFPGAs where the overhead may become prohibitive for implementation or being cost effective. Implementations typically use D-type flip flops (DFFs) which require word lines and bit lines for a sequential approach, as well as row and column decoders.
Therefore, in view of the deficiencies of the prior art it would be advantageous to provide a solution for FPGAs in general, and EFPGAs in particular, that would reduce the overhead associated with the presence of programming support for the configurations of such FPGAs and EFPGAs.